1. Field of the Invention
The present invention relates to a digital delay locked loop. More particularly, the present invention relates to a digital delay locked loop that detects phases according to a specific period signal transmitted by each of a plurality of controllable delay circuits.
2. Description of Related Art
Delay locked loops are mainly used for synchronizing and tracking of clock signals among different circuit systems. For example, in high-speed microprocessors, the delay locked loops are used to eliminate asynchronism between external clock signals and internal clock signals. In communication systems, the delay locked loops are used to recover clocks or data of the systems. Therefore, the delay locked loops are indispensable basic components in many system applications.
FIG. 1 is a basic architectural view of a conventional delay locked loop. Referring to FIG. 1, a conventional delay locked loop 100 forms a feedback mechanism with a phase detector 110, a controller 120, and a delay line 130. The phase detector 110 detects a phase difference between an external clock signal VOUT and an internal clock signal VIN, so as to generate a phase detection code Bf1. The controller 120 can acquire whether the external clock signal VOUT is before or after the internal clock signal VIN according to the phase detection code Bf1. Thus, the delay line 130 can regulate the delay time of the internal clock signal VIN according to a delay control code Bd1 generated by the controller 120. Accordingly, the conventional delay locked loop 100 keeps regulating the external clock signal VOUT until the external clock signal VOUT is synchronous with the internal clock signal VIN by the use of the above feedback mechanism.
However, the conventional delay locked loop 100 adopts a mixed-mode design, which incurs many inevitable problems. For example, the conventional delay locked loop 100 cannot be developed to be highly integrated, and is quite sensitive to variations of process parameters including voltage and temperature. In addition, as the locked time of the conventional delay locked loop 100 is too long, so the power consumption will be excessively high.